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74LCXZ16244 Low Voltage 16-Bit Buffer/Line Driver with 5V Tolerant Inputs and Outputs
September 2000 Revised August 2001
74LCXZ16244 Low Voltage 16-Bit Buffer/Line Driver with 5V Tolerant Inputs and Outputs
General Description
The LCXZ16244 contains sixteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. When VCC is between 0 and 1.5V, the LCXZ12644 is in the high impedance state during power up or power down. This places the outputs in high impedance (Z) state preventing intermittent low impedance loading or glitching in bus oriented applications. The LCXZ16244 is designed for low voltage (2.7V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCXZ16244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.
Features
I 5V tolerant inputs and outputs I Guaranteed power up/down high impedance I Supports live insertion/withdrawal I 2.7V-3.6V VCC specifications provided I 4.5 ns tPD max (VCC = 3.0V), 20 A ICC max I 24 mA output drive (VCC = 3.0V) I Implements patented noise/EMI reduction circuitry I Latch-up performance exceeds 500 mA I ESD performance: Human body model > 2000V Machine model > 200V I Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary)
Ordering Code:
Order Number 74LCXZ16244GX (Note 1) 74LCXZ16244MEA (Note 2) 74LCXZ16244MTD (Note 2) Package Number BGA54A (Preliminary) MS48A MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: BGA package available in Tape and Reel only. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
(c) 2001 Fairchild Semiconductor Corporation
DS500252
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74LCXZ16244
Connection Diagrams
Pin Assignment for SSOP and TSSOP
Pin Descriptions
Pin Names OEn I0-I15 O0-O15 NC Description Output Enable Input (Active LOW) Inputs Outputs No Connect
FBGA Pin Assignments
1 A B C D E F G H J O0 O2 O4 O6 O8 O10 O12 O14 O15 2 NC O1 O3 O5 O7 O9 O11 O13 NC 3 OE1 NC VCC GND GND GND VCC NC OE4 4 OE2 NC VCC GND GND GND VCC NC OE3 5 NC I1 I3 I5 I7 I9 I11 I13 NC 6 I0 I2 I4 I6 I8 I10 I12 I14 I15
Truth Tables
Inputs OE1 Pin Assignment for FBGA L L H Inputs OE2 L L H Inputs OE3 L (Top Thru View) L H Inputs OE4 L L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
Outputs I0-I3 L H X O0-O3 L H Z Outputs I4-I7 L H X O4-O7 L H Z Outputs I8-I11 L H X O8-O11 L H Z Outputs I12-I15 L H X O12-O15 L H Z
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74LCXZ16244
Functional Description
The LCXZ16244 contains sixteen non-inverting buffers with 3-STATE standard outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs.
Logic Diagram
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74LCXZ16244
Absolute Maximum Ratings(Note 3)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE or VCC = 0-1.5V Output in HIGH or LOW State (Note 4) VI < GND VO < GND VO > VCC V mA mA mA mA mA
-0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 -50 -50 +50 50 100 100 -65 to +150
C
Recommended Operating Conditions (Note 5)
Symbol VCC VI VO IOH/IOL TA Supply Voltage Input Voltage Output Voltage Output Current Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V-2.0V, VCC = 3.0V HIGH or LOW State 3-STATE or VCC = OFF VCC = 3.0V - 3.6V VCC = 2.7V - 3.0V Parameter Operating Min 2.7 0 0 0 Max 3.6 5.5 VCC 5.5 Units V V V mA
24 12 -40
0 85 10
C
ns/V
t/V
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 4: IO Absolute Maximum Rating must be observed. Note 5: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = -100 A IOH = -12 mA IOH = -18 mA IOH = -24 mA VOL LOW Level Output Voltage IOL = 100 A IOL = 12 mA IOL = 16 mA IOL = 24 mA II IOZ IOFF IPU/PD ICC ICC Input Leakage Current 3-STATE Output Leakage Power-Off Leakage Current Power Up/Down 3-STATE Output Current Quiescent Supply Current Increase in ICC per Input 0 VI 5.5V 0 VO 5.5V VI = VIH or VIL VI or VO = 5.5V VO = 0.5V to VCC VI = GND or VCC VI = VCC or GND 3.6V VI, VO 5.5V (Note 6) VIH = VCC -0.6V
Note 6: Outputs disabled or 3-STATE only.
Conditions
VCC (V) 2.7 - 3.6 2.7 - 3.6 2.7 - 3.6 2.7 3.0 3.0 2.7 - 3.6 2.7 3.0 3.0 2.7 - 3.6 2.7 - 3.6 0 0 - 1.5 2.7 - 3.6 2.7 - 3.6 2.7 - 3.6
TA = -40C to +85C Min 2.0 0.8 VCC - 0.2 2.2 2.4 2.2 0.2 0.4 0.4 0.55 5.0 5.0 10 5.0 225 225 500 Max
Units V V
V
V
A A A A A A
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74LCXZ16244
AC Electrical Characteristics
TA = -40C to +85C, RL = 500 Symbol Parameter VCC = 3.3V 0.3V CL = 50 pF Min tPHL tPLH tPZL tPZH tPLZ tPHZ tOSHL tOSLH Output to Output Skew (Note 7) Output Disable Time Propagation Delay Data to Output Output Enable Time 1.0 1.0 1.0 1.0 1.0 1.0 Max 4.5 4.5 5.5 5.5 5.4 5.4 1.0 1.0 VCC = 2.7V CL = 50 pF Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 5.2 5.2 6.3 6.3 5.7 5.7 ns ns ns ns Units
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 50 pF, VIH = 3.3V, VIL = 0V VCC (V) 3.3 3.3 TA = 25C Typical 0.8 -0.8 V V Units
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Conditions VCC = Open, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC, f = 10 MHz Typical 7 8 20 Units pF pF pF
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74LCXZ16244
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) VI 6V for VCC = 3.3V, 2.7V CL 50 pF
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f = 1 MHz, tr = tf = 3 ns) Symbol Vmi Vmo Vx Vy VCC 3.3V 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 2.7V
trise and tfall
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74LCXZ16244
Schematic Diagram Generic for LCX Family
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74LCXZ16244
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary
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74LCXZ16244
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
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74LCXZ16244 Low Voltage 16-Bit Buffer/Line Driver with 5V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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